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Diffstat (limited to 'student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v')
| -rw-r--r-- | student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v new file mode 100644 index 0000000..b064bbe --- /dev/null +++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v @@ -0,0 +1,76 @@ +// -------------------------------------------------------------------- +// Copyright (c) 2008 by Terasic Technologies Inc. +// -------------------------------------------------------------------- +// +// Permission: +// +// Terasic grants permission to use and modify this code for use +// in synthesis for all Terasic Development Boards and Altera Development +// Kits made by Terasic. Other use of this code, including the selling +// ,duplication, or modification of any portion is strictly prohibited. +// +// Disclaimer: +// +// This VHDL/Verilog or C/C++ source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Terasic provides no warranty regarding the use +// or functionality of this code. +// +// -------------------------------------------------------------------- +// +// Terasic Technologies Inc +// 356 Fu-Shin E. Rd Sec. 1. JhuBei City, +// HsinChu County, Taiwan +// 302 +// +// web: http://www.terasic.com/ +// email: support@terasic.com +// +// -------------------------------------------------------------------- +// +// Major Functions: sdr_data_path +// +// -------------------------------------------------------------------- +// +// Revision History : +// -------------------------------------------------------------------- +// Ver :| Author :| Mod. Date :| Changes Made: +// V1.0 :| Johnny Fan :| 08/04/22 :| Initial Revision +// -------------------------------------------------------------------- + +module sdr_data_path( + CLK, + RESET_N, + DATAIN, + DM, + DQOUT, + DQM + ); + +`include "Sdram_Params.h" + +input CLK; // System Clock +input RESET_N; // System Reset +input [`DSIZE-1:0] DATAIN; // Data input from the host +input [`DSIZE/8-1:0] DM; // byte data masks +output [`DSIZE-1:0] DQOUT; +output [`DSIZE/8-1:0] DQM; // SDRAM data mask ouputs +reg [`DSIZE/8-1:0] DQM; + + + +// Allign the input and output data to the SDRAM control path +always @(posedge CLK or negedge RESET_N) +begin + if (RESET_N == 0) + DQM <= `DSIZE/8-1'hF; + else + DQM <= DM; +end + +assign DQOUT = DATAIN; + +endmodule + |